1. Technical Field
Various embodiments generally relate to a semiconductor apparatus, and more particularly, to a data write circuit of a semiconductor apparatus.
2. Related Art
FIG. 1 is a block diagram showing a conventional data write circuit 1 of a semiconductor apparatus.
Referring to FIG. 1, the conventional data write circuit 1 of a semiconductor apparatus includes a plurality of pads DQS, DQSB and DQ0 to DQi, a plurality of buffers BUF, a plurality of setup/hold delays S/H DLY, a plurality of data latch blocks, and a plurality of data alignment blocks.
In the conventional art, a pair of data strobe signals DQS and DQSB are inputted through the plurality of pads DQS and DQSB, and the data is inputted through the plurality of pads DQ0 to DQi.
The data inputted through the plurality of pads DQ0 to DQi are transferred to the data latch blocks after being tuned in the delay times thereof through the plurality of respective setup/hold delays S/H DLY. Additionally, the data outputted through the plurality of pads DQ0 to DQi is received by buffers BUF, the buffers BUF also receiving a reference voltage VREF and outputting to the respective setup/hold delays S/H DLY.
The data latch blocks latch the data according to a pair of data strobe signals DQSR and DQSF respectively having passed through the buffers BUF. The data latch blocks include flip-flops DFF and a latch LATCH.
Thereafter, the data latched by the data latch blocks are aligned through the data alignment blocks.
The data strobe signal DQS is used as a signal for latching the data simultaneously inputted through the plurality of pads DQ0 to DQi.
Accordingly, since the load of the signal path of the data strobe signal DQS is larger than the load of the signal path of each of the plurality of pads DQ0 to DQi, a difference exists between the delay times of the two signal paths.
In the conventional art, in order to compensate for the difference between the delay times of the two signal paths, the plurality of setup/hold delays S/H DLY are configured.
However, while the load of the signal path of the data strobe signal DQS is owing to the RC component (resistance and capacitance component) of a signal line and the load of a gate logic, nearly most of the load of each of the setup/hold delays S/H DLY is owing to the load of a gate logic.
Therefore, if a variation occurs in PVT (process, voltage and temperature), a difference occurs between the delay of the signal path of the data strobe signal DQS and the delay of a data path, that is, the delay of the setup/hold delay S/H DLY which has a fixed value. Consequently, as write data setup/hold timing is lopsided, a problem is caused in that data write performance is likely to deteriorate.